Apparatus for providing distance protection and distance measurement for a high voltage transmission line

ABSTRACT

a protective relay for detecting faults in electrical power distribution system generates a signal Δi(t) which is substantially equal to the magnitude of the power distribution system current i measured at a first time subtracted from the magnitude of the power distribution system current i measured at a second time, the second time occurring later than the first time. The signal Δi(t) is utilized to generate measurement of the distance of a fault to the relay and is also utilized to generate operate signals if the fault occurs within the zone protected by the relay.

BACKGROUND OF THE INVENTION

The present invention relates to protective systems for use in ACelectrical power distribution systems and more particularly to distancerelays for AC electrical power transmission line protection.

Distance relays are well known in the art of protective relaying. Forexample, reference may be had to "The Art and Science of ProtectiveRelaying", Mason, published by John Wiley and Son, Inc. (1956),particularly 115 to Chapter 14. Exemplary types of distance relays aredisclosed in U.S. Pat. No. 4,034,269, issued to S. B. Wilkinson, on July5, 1977; U.S. Pat. No. 4,420,788, issued to S. B. Wilkinson and G. E.Alexander on Dec. 13, 1983; and U.S. Pat. No. 4,405,966, issued toLeonardo Cavero, the inventor of the present invention, on Sept. 20,1983. All these patents are assigned to the assignee of the presentinvention and are incorporated by reference in the present applicationas if fully set forth herein.

Distance relays are utilized in protective systems for AC powertransmission lines to detect faults within protected zones or portionsof the transmission lines. If such a fault is detected within therelay's zone or reach, the distance relay will enable operation of acircuit breaker in order to trip the faulted phase or phases.

Phase distance relays are utilized to detect phase to phase faultswithin a protected zone or portion of a transmission line. If such afault is detected within the zone or reach of this type of distancerelay, the phase distance relay will initiate a signal which will beused to cause the operation of a three pole circuit breaker to trip allthree phases of the transmission line. This is to be contrasted with aground distance relay which detects faults between a phase and ground,again within a designated zone or reach; and, upon detection of such afault, generates a signal which enables the operation of a circuitbreaker to trip the faulted phase only.

As indicated above, each particular distance relay should only detectfaults within its protected zone or reach. The parameters of a distancerelay are commonly selected to correspond to the parameters of thetransmission line. For example, the parameters are selected to provide aforward reach that may correspond to the forward distance of theprotected zone of transmission line under protection of the particularrelay. It is desired that the distance relay operate within its selectedforward reach thereby confining the protection of a particular distancerelay to the selected zone within a protected system.

The desired operation of the distance relay may be hindered by theinability to distinguish between internal and external faults. Internalfaults are hose which occur within the protected zone or reach of therelay, whereas external faults are those which occur outside the zone orrelay reach. For example, errors in measuring fault resistance can causethe fault to appear further away from or closer to the distance relaylocation than it actually is; situations which, in the worse case, couldprevent the operation of the distance relay on a fault occurring withinits zone or reach, or could cause the relay to misoperate for a faultexternal to the protected zone or reach.

Although distance relays have, in the past, been used to detect faultswithin a predetermined protected zone or reach of the relay, such relayshave not been able to provide a determination of the actual location ofthe fault; that is, the distance from the relay at which the faultoccurred. The ability to determine the location of the fault in terms ofdistance from the relay enhances the utility of a distance relay.

Accordingly, it is an object of the present invention to provide adistance relay with improved discrimination between internal andexternal faults thereby increasing the reliability of the relayoperation and the security of the protection system.

It is another object of the present invention to provide a distancerelay for detecting faults in a protected zone of an AC electrical powertransmission line, which relay determines the distance to the fault.

It is yet another object of the present invention to provide a distancerelay with a capability for improved fault resistance determination.

It is a further object of the present invention to provide a distancerelay which substantially eliminates the adverse effects on faultdistance determination due to fault current components from multiplesources connected to the AC power transmission line.

It is still another object of the present invention to provide adistance relay which eliminates adverse effects of prefault load currenton fault distance determination.

These and other objects of the present invention will become apparent tothose skilled in the art upon consideration of the following descriptionof the invention.

SUMMARY OF THE INVENTION

The present invention comprises a distance relay for detecting faultswithin a predetermined protected zone of an AC electrical powertransmission line and for measuring the distance to detected faults. Thedistance relay includes means for detecting a fault current andsubtracting prefault current therefrom.

The features of the invention believed to be novel, are set forthparticularly in the appended claims. The invention itself, however, bothas to its organization and operation, together with further objects andadvantages thereof, may best be understood by reference to the followingdescription in conjunction with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a one line, block diagram of a current and voltage processingportion of a preferred embodiment of the present invention.

FIG. 2 is a block diagram of a first operate signal generation portionof the preferred embodiment of the present invention, utilizing voltageand current signals generated by that portion depicted in FIG. 1.

FIG. 3 is a block diagram of a distance measurement portion of thepreferred embodiment of the present invention, utilizing voltage andcurrent signals generated by the portion depicted in FIG. 1.

FIG. 4 is of a block diagram of a second operate signal generationportion of the preferred embodiment of the present invention, utilizingvoltage and current signals generated by that portion depicted in FIG.1.

FIG. 5 is a block diagram of a trip signal generation portion of thepreferred embodiment of the present invention, utilizing the first andsecond operate signals generated by that portion depicted in FIGS. 2 and4 respectively.

FIG. 6 depicts the characteristic of the preferred embodiment of therelay of the present invention plotted on an L-R diagram.

FIG. 7 is a block diagram of a third operate signal generation portionof the preferred embodiment of the present invention, utilizing a deltacurrent signal generated by that portion depicted in FIG. 1 and signalsgenerated by the second operate signal generation portion depicted inFIG. 4.

FIG. 8 is a one line, block diagram of an current and voltage processingportion of an alternate preferred embodiment of the present invention.

FIG. 9 is a block diagram of a distance impedance measurement portion ofthe alternate preferred embodiment of the present invention, utilizingvoltage and current signals generated by that portion depicted in FIG.8.

FIG. 10 is a block diagram of a distance protection portion of thealternate preferred embodiment of the present invention, utilizingvoltage and current signals generated by that portion depicted in FIG.8.

FIG. 11 is a block diagram of a distance protection, resistance reachand measurement portion of the alternate preferred embodiment of thepresent invention, utilizing voltage and current signals generated bythat portion depicted in FIG. 8.

FIG. 12 is a block diagram of a trip signal generation portion of thealternate preferred embodiment of the present invention, utilizing theoperate signals generated by that portion depicted in FIGS. 10 and 11.

FIG. 13 depicts the characteristic of the alternate preferred embodimentof the relay of the present invention plotted on a L-R diagram.

FIG. 14 is a block diagram of a preferred embodiment of a faultresistance measurement portion of the present invention.

FIG. 15 is a block diagram of an alternate preferred embodiment of aresistance measurement portion of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, there is shown an alternating current electricpower transmission line, generally designated 10. Although suchalternating current electrical power transmission lines normallycomprise three phases and ground, for purposes of simplicity andclarity, the following detailed description will be described withrespect to the A phase (A) and ground (G). It should be understood thatthe following description also applies with respect to the B and the Cphase, as well as relays connected between phases.

Associated with A phase is means 12 for sensing current in that phase aswell as means 14 for sensing voltage on that phase. As is well known tothose skilled in the protective relaying and power transmission art,current sensing means 12 may be a current transformer and voltagesensing means 14 may be a step down potential transformer. Also, acurrent sensing means may be associated with each phase as well as aseparate voltage sensing means associated with each phase. However, itis to be understood that although a specific type of current and voltagesensing scheme is depicted in FIG. 1, other schemes known in the art maybe substituted for that depicted; the purpose being to obtain signalswhich are related to each phase voltage and each phase current.

The output from the current sensing means 12, which is a signal i_(A)(t) proportional to the current flowing in the A phase, is coupled tothe input of a first low pass filter 16. The output of the voltagesensing means 14, which is a signal v_(A) (t) proportional to the phaseA to ground voltage, is coupled to the input of a second low pass filter18. In the preferred embodiment, the first 16 and second 18 low passfilters each preferably have a frequency cut off of approximately 500 Hzin order to filter out transients and other spurious signals havingfrequencies which exceed 1 KHz, while passing, substantially unchanged,signals at the system frequency which is typically 50 Hz or 60 Hz.Consequently, the output signal i_(A) (t) from the first filter 16 isthe filtered input signal i_(A) (t), and the output signal v_(A) (t)from the second filter 18 is the filtered input signal v_(A) (t).

The output v_(A) (t) of the second low pass filter 18 is coupled to theinput of a first analog to digital (A/D) converter 20. In the preferredembodiment, the first A/D converter 20 samples the magnitude of theinput signal at a predetermined rate which i the preferred embodiment,is twenty samples per cycle in 50 Hz systems and sixteen samples percycle in 60 Hz systems. The magnitude of each sample is converted into adigital signal having a value corresponding to such magnitude.Consequently, the output v_(A) (t) of the first A/D converter 20 is adigitized version of the analog input signal.

The output of the first low pass filter 16 is coupembodiment, the secondA/D converter 22 is of the same type and performs the same function asthat previously described with respect to the first A/D converter 20.The output i_(A) (t) of the second A/D converter 22, which is adigitized version of the input signal, is coupled to the input of abuffer 24, a positive input of a first digital subtraction circuit 26,the input of a first differentiator 28 and the input of a first scaler30. In the preferred embodiment, the buffer 24 comprises a memory forstoring the digitized input signal i_(A) (t) for a time k/f where k is apredetermined constant and f is the system frequency, typically 50 Hz or60 Hz. Accordingly, the output of the buffer 24 is the signal i_(A)(t-k/f). When k=1, the output of the buffer 24 is equal to the magnitudeof i_(A) at a point one cycle prior to the input i_(A) (t). In thepreferred embodiment, the output i_(A) (t-k/f) of buffer 24 is the inputsignal i_(A) (t) which has been delayed five cycles at the fundamentalsystem frequency; that is, 100 milliseconds in a 50 Hz system and 83.333milliseconds in a 60 Hz system.

The output i_(A) (t-k/f) of the buffer 24 is coupled to a negative inputof the first digital subtraction circuit 26. In the preferredembodiment, the first digital subtraction circuit 26 is a circuit whoseoutput is a digital signal Δi_(A) (t) having a digital value equal tothe magnitude of the digital value of the input signal applied to thepositive input minus the value of the signal applied to the negativeinput. Since the signal i_(A) (t) is applied to the positive input andthe signal i_(A) (t-k/f) is applied to the negative input, the outputsignal, Δi_(A) (t) is equal to i_(A) (t)-i_(A) (t-k/f). The outputΔi_(A) (t) of the digital subtraction circuit 26 is coupled to the inputof a second differentiator 32 and one input of a first two-input adder34. In the preferred embodiment, the first 28 and second 32differentiators each measures and stores the magnitude of the inputsignal at a first time t₁ and again at a second time t₃, then subtractsthe magnitude measured at t₁ from the magnitude measured at t₃ anddivides the result by the magnitude of time t₃ minus time t₁.Consequently, the output of the second digital differentiator 32 is asignal dΔi_(A) (t)/dt at a time t₂, having a value substantially equalto the differential, with respect to time, of the input signal Δi_(A)(t).

The output of the second digital differentiator 32 is coupled to theinput of a second scaler 36. The second scaler 36 is a circuit whoseoutput is a digital signal having a magnitude equal to the input signaldΔi_(A) (t)/dt multiplied by a predetermined scaler function which, inthe preferred embodiment is tan α/2 πf, where f is the fundamentalsystem frequency, typically 50 Hz or 60 Hz, and tan α is a quantitywhich is a function of the particular power system in which the distancerelay of the present invention is used. Consequently the output of thesecond scaler 36 is ##EQU1##

The output of the second scaler 36 is coupled to the second input of thefirst two-input adder 34. The first two-input adder 34 is a circuitwhose output is a digital signal i_(f) (t) having a magnitude which isequal to the digital sum of the input signals which are Δi_(A) (t) and##EQU2## Consequently, the output i_(f) (f) of the first two-input adder34 is equal to ##EQU3##

The output of the first differentiator 28 is a digital signal di_(A)(t)/dt whose magnitude is the differential respect to time of the inputsignal i_(A) (t). The output di_(A) (t)/dt of the first differentiator28 is coupled to the input of a third scaler 38. The third scaler 38 isof the same type as that previously described with respect to the first30 and second 36 scalers, having a digital output signal whose magnitudeis equal to the input di_(A) (t)/dt multiplied by a predeterminedscaling function which, in the preferred embodiment, is L. Consequently,the output of the third scaler 38 is _(L) di_(A) (t)/dt. The magnitudeof L is selected to be substantially equal to the line inductance permile of the particular power system in which the relay of the presentinvention is used. The output _(L) di_(A) (t)/dt of the third scaler 38is coupled to one input of a second two input adder 40.

The output of the first scaler 30 is a digital signal whose magnitude isequal to the input signal i_(A) (t) multiplied by a predeterminedscaling function which, in the preferred embodiment, is R. Consequently,the output of the first scaler 30 is Ri_(A) (t). The magnitude of R isselected to be substantially equal to the line resistance per mile ofthe particular power system in which the relay of the present inventionis used. The output Ri_(A) (t) of the first scaler 30 is coupled to thesecond input of the second two input adder 40. The second two inputadder 40 is the same type as that previously described with respect tothe first two input adder 34, having an output signal whose magnitude isequal to the sum of the inputs Ri_(A) (t) and _(L) di_(A) (t)/dt.Accordingly, v_(r) (t) is equal to ##EQU4##

Referring now to FIG. 2, the output signal i_(f) (t) from the firsttwo-input adder 34 (see FIG. 1) is coupled to the input of the firstsampler/buffer circuit 42. The output v_(r) (t) from the secondtwo-input adder 40 (see FIG. 1) is coupled to the input of a secondsampler/buffer circuit 44. The output v_(A) (t) of the first A/Dconverter 20 (see FIG. 1) is coupled to the input of a thirdsampler/buffer circuit 46. In the preferred embodiment, the first 42,second 44 and third 46 sampler/buffer circuits each have two outputs,the first of which is equal to the magnitude of the input signal sampledat a first time t₁, and the second of which is equal to the magnitude ofthe input signal sampled at a second time t₂. Consequently, the outputsof the first sampler/buffer circuit 42 is a first signal i_(f) (t₁)which is the input signal i_(f) (t) sampled at time t₁ ; and the secondoutput is a signal i_(f) (t₂) which is equal to the input signal i_(f)(t) sampled at time t₂.

Similarly, the outputs of the second sampler/buffer circuit 44 comprisea first signal v_(r) (t₁) which is equal to the input signal v_(r) (t)sampled at the first time t₁ ; and a second signal v_(r) (t₂) which isequal to the input signal v_(r) (t) sampled at the second time t₂. Theoutputs of the third sampler/buffer circuit 46 comprise a first signalv_(A) (t₁) which is equal to the input signal v_(A) (t) sampled at thefirst time t₁ ; and a second signal v_(A) (t₂) which is equal to theinput signal v_(A) (t) sampled at the second time t₂.

The output signal i_(f) (t₁) from the first sampler/buffer circuit 42 iscoupled to one input of a first two-input multiplier 48 and one input ofa second two-input multiplier 50. The output signal i_(f) (t₂) from thefirst sampler/buffer circuit 42 is coupled to one input of a thirdtwo-input multiplier 52 and one input of a fourth two-input multiplier54. The output signal v_(r) (t₁) from the second sampler/buffer circuit44 is coupled to the second input of the third two-input multiplier 52.The output signal v_(r) (t₂) from the second sampler/buffer circuit 44is coupled to the second input of the first two-input multiplier 48. Theoutput signal v_(A) (t₁) from the third sampler/buffer circuit 46 iscoupled to the second input of the fourth two-input multiplier 54. Theoutput signal v_(A) (t₂) from the third sampler/buffer circuit 46 iscoupled to the second input of the second two-input multiplier 50.

In the preferred embodiment, the first 48, second 50, third 52 andfourth 54 two-input multipliers are each digital multipliers producing adigital output signal having a magnitude which is equal to the magnitudeof the first input signal multiplied by the magnitude of the secondinput signal. Consequently, the output of the first multiplier 48 is thesignal v_(r) (t₂)i_(f) (t₁); the output of the second multiplier circuit50 is the signal v_(A) (t₂)i_(f) (t₁); the output of the thirdmultiplier 52 is the signal v_(r) (t₁)i_(f) (t₂); and the output of thefourth multiplier 54 is the signal vhd Al (t₁)i_(f) (t₂).

The output of the first multiplier circuit 48 is coupled to a negativeinput of a second digital subtraction circuit 60. The output of thesecond multiplier circuit 50 is coupled to a negative input of a thirddigital subtraction circuit 62. The output of the third multipliercircuit 52 is coupled to a positive input of the second digitalsubtraction circuit 60 The output of the fourth multiplier circuit 54 iscoupled to a positive input of the third digital subtraction circuit 62.In the preferred embodiment the second 60 and third 62 digitalsubtraction circuits are of the same type as the previously describedfirst digital subtraction circuit 26, each producing a digital outputsignal whose magnitude is equal to the magnitude of the signal appliedto the positive input minus the magnitude of the signal applied to thenegative input. Consequently, the output of the second digitalsubtraction circuit 60 is the signal S₁ which is equal to v_(r)(t₁)i_(f) (t₂)-v_(r) (t₂)i_(f) (t₁); and the output of the third digitalsubtraction circuit 26 is the signal S₂ which is equal to v_(A)(t₁)i_(f) (t₂)-v_(A) (t₂)i_(f) (t₁).

The output signal S₁ from the second digital subtraction circuit 60 iscoupled to the input of a fourth scaler circuit 64. The fourth scalercircuit 64 is preferably of the same type as that previously describedwith respect to the first 30, second 36 and third 38 scaler circuits,having an output which is equal to the input multiplied by apredetermined scaling function. In the preferred embodiment, the scalingfunction of the fourth scaler circuit 64 is the quantity n_(set) whichis a constant determined by the desired relay reach. Consequently, theoutput of the fourth scaler circuit 64 is the signal

    n.sub.set {v.sub.r (t.sub.1)i.sub.f (t.sub.2)-v.sub.r (t.sub.2)i.sub.f (t.sub.1)}

or n_(set) S₁.

The output of the fourth scaler circuit 64 is coupled to a first inputof a first two-input comparator circuit 66. The output of the thirddigital subtraction circuit 62 is coupled to a second input of the firsttwo-input comparator circuit 66. The first two-input comparator circuit66 is a digital comparator which generates an output signal when themagnitude of the signal applied to the first input exceeds the magnitudeof the signal applied to the second input. Consequently, the firsttwo-input comparator circuit 66 generates an output signal when themagnitude of the signal n_(set) {v_(r) (t₁)i_(f) (t₂)-v_(r) (t₂)i_(f)(t₁)} exceeds the magnitude of the signal

    {v.sub.A (t.sub.1)i.sub.f (t.sub.2)-v.sub.A (t.sub.2)i.sub.f (t.sub.1)} or n.sub.set S.sub.1 >S.sub.2.

The output of the first two-input comparator circuit 66 is coupled tothe input of a first counter 68. In the preferred embodiment, the firstcounter 68 provides a count signal upon receipt of a signal from thefirst two-input comparator circuit 66. The count signal is incrementedby one count if the signal from the circuit 66 is present during thenext succeeding sampling interval; otherwise, the count signal is resetto zero. The count signal is incremented by one count upon receipt of asignal from circuit 66 during each succeeding sampling interval. Thecount signal is reset to zero following any sampling interval duringwhich a signal is not received from circuit 66.

The count signal from the first counter 68 is coupled to the input of afirst comparator circuit 70. The first comparator circuit 70 generatesan output signal O₁, which is a first operate signal in the preferredembodiment described herein, when the magnitude of the input signalexceeds a predetermined value. Consequently, the first comparatorcircuit 70 will generate the first operate signal O₁ when the magnitudeof the count signal from the counter 68 exceeds a predetermined value,for example three in the preferred embodiment. This means that in thepreferred embodiment, the first operate signal O₁ will be generated upondetection of a signal from the first two-input comparator circuit 66during at least three consecutive sampling intervals.

Referring now to FIG. 3, the output signal Δi_(A) (t) from the firstdigital subtraction circuit 26 (see FIG. 1) is coupled to the input of afourth sampler/buffer circuit 202. The output V_(r) (t) from the secondtwo input adder 40 (see FIG. 1) is coupled to the input of a fifthsampler/buffer circuit 204. The output v_(A) (t) of the first A/Dconverter 20 (see FIG. 1) is coupled to the input of a sixthsampler/buffer circuit 206. In the preferred embodiment, the fourth 202,fifth 204 and sixth 206 sampler/buffer circuits are of the same type asthe first 42, second 44 and third 46 sampler/buffer circuits previouslydescribed. Each has two outputs, the first of which is equal to themagnitude of the input signal sampled at the first time t₁, and thesecond of which is equal to the magnitude of the input signal sampled atthe second time t₂. Consequently, the outputs of the fourthsampler/buffer circuit 202 is a first signal Δi_(A) (t₁) which is theinput signal Δi_(A) (t) sampled at the first time t₁ ; and the secondoutput is a signal Δi_(A) (t₂) which is equal to the input signal Δi_(A)(t) sampled at the second time t₂.

Similarly, the outputs of the fifth sampler/buffer circuit 204 comprisea first signal V_(r) (t₁) which is equal to the input signal V_(r) (t)sampled at the first time t₁ ; and a second signal V_(r) (t₂) which isequal to the input signal V_(r) (t) sampled at the second time t₂. Theoutputs of the sixth sampler/buffer circuit 206 comprise a first signalv_(A) (t₁) which is equal to the input signal v_(A) (t) sampled at thefirst time t₁ ; and a second signal v_(A) (t₂) which is equal to theinput signal v_(A) (t) sampled at the second time t₂.

The signal Δi_(A) (t₁) output from the fourth sampler/buffer circuit 202is coupled to one input of a fifth two-input multiplier 208 and oneinput of a sixth two-input multiplier 210. The signal Δi_(A) (t₂) outputfrom the fourth sampler/buffer circuit 202 is coupled to one input of aseventh two-input multiplier 212 and one input of an eighth two-inputmultiplier 214. The V_(r) (t₁) signal output from the fifthsampler/buffer circuit 204 is coupled to the second input of the seventhtwo-input multiplier 212. The signal V_(r) (t₂) output from the fifthsampler/buffer circuit 204 is coupled to the second input of the fifthtwo-input multiplier 208. The signal v_(A) (t₁) output from the sixthsampler/buffer circuit 206 is coupled to the second input of the eighthtwo-input multiplier 214. The signal v_(A) (t₂) output from the sixthsampler/buffer circuit 206 is coupled to the second input of the sixthtwo-input multiplier 210.

In the preferred embodiment, the fifth 208, sixth 210, seventh 212 andeighth 214 two-input multipliers are the same type as the first 48,second 50, third 52 and fourth 54 two-input multipliers previouslydescribed. Each two-input multiplier produces a digital output signalhaving a magnitude which is equal to the magnitude of the first inputsignal multiplied by the magnitude of the second input signalConsequently, the output of the fifth multiplier 208 is the signal V_(r)(t₂)Δi_(A) (t₁); the output of the sixth multiplier circuit 210 is thesignal v_(A) (t₂)Δi_(A) (t₁): the output of the seventh multiplier 212is the signal V_(r) (t₁)Δi_(A) (t₂); and the output of the eighthmultiplier 214 is the signal v_(A) (t₁)Δi_(A) (t₂).

The output of the fifth multiplier circuit 208 is connected to anegative input of a fourth digital subtraction circuit 216. The outputof the sixth multiplier circuit 210 is coupled to a negative input of afifth digital subtraction circuit 218. The output of the seventhmultiplier circuit 212 is coupled to a positive input of the fourthdigital subtraction circuit 216. The output of the eighth multipliercircuit 214 is coupled to a positive input of the fifth digitalsubtraction circuit 218. In the preferred embodiment, the fourth 216 andfifth 218 digital subtraction circuits are of the same type as thepreviously described first 26, second 60 and third 62 digitalsubtraction circuits, with each producing a digital output signal whosemagnitude is equal to the magnitude of the signal applied to thepositive input minus the magnitude of the signal applied to the negativeinput. Consequently, the output signal S₃ of the fourth digitalsubtraction circuit 216 is equal to V_(r) (t₁)Δi_(A) (t₂)-V_(r)(t₂)Δi_(A) (t₁); and the output signal S₄ of the fifth digitalsubtraction circuit 218 is equal to V_(A) (t₁)Δi_(A) (t₂)-V_(A)(t₂)Δi_(A) (t₁).

The output signal S₃ of the fourth digital subtraction circuit 216 iscoupled to the divisor input of a digital divider circuit 220. Theoutput signal S₄ of the fifth digital subtraction circuit 218 is coupledto a dividend input of the digital divider 220. The output n from thedivider circuit 220 is a digital signal whose magnitude is equal to thequentin of the digital signal S₄ applied to the dividend input dividedby the digital signal S₃ applied to the divisor input. The magnitude ofthe signal n is a function of the distance from the relay to the faultand is equal to ##EQU5##

Referring now to FIG. 4, the output signal Δi_(A) (t) from the firstdigital subtraction circuit 26 (see FIG. 1) is coupled to the input of aseventh sampler/buffer circuit 402. The output V_(r) (t) from the secondtwo-input adder 40 (see FIG. 1) is coupled to the input of an eighthsampler/buffer circuit 404. The output v_(A) (t) of the first A/Dconverter 20 (see FIG. 1) is coupled to the input of a ninthsampler/buffer circuit 406. In the preferred embodiment, the seventh402, eighth 404 and ninth 406 sampler/buffer circuits are of the sametype as the first 42, second 44, third 46, fourth 202, fifth 204 andsixth 206 sampler/buffer circuits previously described. Each has twooutputs, the first of which is equal to the magnitude of the inputsignal sampled at the first time t₁, and the second of which is equal tothe magnitude of the input signal sampled at the second time t₂.Consequently, the outputs of the seventh sampler/buffer circuit 402 is afirst signal Δi_(A) (tl) which is the input signal Δi_(A) (t) sampled atthe first time t₁ ; and the second output is a signal Δi_(A) (t₂) Whichis equal to the input signal Δi_(A) (t) sampled at the second time t₂.

Similarly, the outputs of the eighth sampler/buffer circuit 404comprises a first signal V_(r) (t₁) which is equal to the input signalV_(r) (t) sampled at the first time t₁ ; and a second signal V_(r) (t₂)which is equal to the input signal V_(r) (t) sampled at the second timet₂. The outputs of the ninth sampler/buffer circuit 406 comprises afirst signal v_(A) (t₁) which is equal to the input signal v_(A) (t)sampled at the first time t₁ ; and a second signal v_(A) (t₂) which isequal to the input signal v_(A) (t) sampled at the second time t₂.

The signal Δi_(A) (t₁) output from the seventh sampler/buffer circuit402 is coupled to one input of a two-input multiplier 408. The signalΔi_(A) (t₂) output from the seventh sampler/buffer circuit 402 iscoupled to one input of a tenth two-input multiplier 410. The V_(r) (t₁)signal output from the eighth sampler/buffer circuit 404 is coupled tothe second input of the tenth two-input multiplier 410 and to one inputof an eleventh two-input multiplier 412. The V_(r) (t₂) signal outputfrom the eighth sampler/buffer circuit 404 is coupled to a second inputof the ninth two-input multiplier 408 and one input of a twelfthtwo-input multiplier 414. The v_(A) (t₁) signal output from the ninthsampler/buffer circuit 406 is coupled to a second input of the twelfthtwo-input multiplier 414. The v_(A) (t₂) signal output from the ninthsampler/buffer circuit 406 is coupled to a second input of the eleventhtwo-input multiplier 412.

In the preferred embodiment, the ninth 408, tenth 410, eleventh 412 andtwelfth 414 two-input multipliers are the same type as the first 48through eighth 214 two-input multipliers previously described. Eachtwo-input multiplier produces a digital output signal having a magnitudewhich is equal to the magnitude of the first input signal multiplied bythe magnitude of the second input signal. Consequently, the output ofthe ninth multiplier 408 is the signal v_(r) (t₂) Δi_(A) (t₁); theoutput of the tenth multiplier 410 is the signal v_(r) (t₁)Δi_(A) (t₂);the output of the eleventh multiplier 412 is the signal v_(A) (t₂)v_(r)(t₁); and the output of the twelfth multiplier 414 is the signal v_(A)(t₁)v_(r) (t₂).

The output of the ninth multiplier circuit 408 is connected to apositive input of a sixth digital subtraction circuit 416. The output ofthe tenth multiplier circuit 410 is coupled to a negative input of thesixth digital subtraction circuit 416. The output of the eleventhmultiplier circuit 412 is coupled to a negative input of a seventhdigital subtraction circuit 418. The output of the twelfth multipliercircuit 414 is coupled to the positive input the seventh digitalsubtraction circuit 418. In the preferred embodiment, the sixth 416 andseventh 418 digital subtraction circuits are of the same type as thepreviously described first 26, second 60, third 62, fourth 216 and fifth218 digital subtraction circuits, with each providing a digital outputsignal whose magnitude is equal to the magnitude of the signal appliedto the positive input minus the magnitude of the signal applied to thenegative input. Consequently, the output signal S₅ of the sixth digitalsubtraction circuit 416 is equal to v_(r) (t₂) Δi_(A) (t₁)-v_(r)(t₁)Δi_(A) (t₂); and the output signal S₆ of the seventh digitalsubtraction circuit 418 is equal to v_(A) (t₁)V_(r) (t₂)-v_(A) (t₂)V_(r)(t₁).

The output signal S₅ of the sixth digital subtraction circuit 416 iscoupled to the divisor input of a second digital divider circuit 420.The output signal S₆ of the seventh digital subtraction circuit 418 iscoupled to a dividend input of the second digital divider 420. In thepreferred embodiment, the second digital divider 420 is the same type asthe previously described first digital divider circuit 220; having anoutput signal which is a digital signal whose magnitude is equal to thequotient of the digital signal S₆ applied to the dividend input dividedby the digital signal S₅ applied to the divisor input. Consequently, theoutput R_(fA) from the second divider circuit 420 is equal to ##EQU6##The signal R_(fA) is a function of the fault resistance; that is, themagnitude of R_(fA) is proportional to the magnitude of the faultresistance measured at the relay location and the angle of the signalR_(fA) is substantially equal to the fault resistance angle.

The output signal S₅ of the sixth digital subtraction circuit 416 isalso coupled to the input of a fifth scaler circuit 422. The fifthscaler circuit 422 is preferably of the same type as that previouslydescribed with respect to the first 30, second 36, third 38 and fourth64 scaler circuits, having an output which is equal to the inputmultiplied by a predetermined scaling function. In the preferredembodiment, the scaling function of the fifth scaler circuit 22 is thequantity R_(SET) which is a constant determined by the desired relayreach. Consequently, the output of the fifth scaler circuit 222 is thesignal

    R.sub.SET [Δi.sub.A (t.sub.1)V.sub.r (t.sub.2)-Δi.sub.A (t.sub.2)V.sub.r (t.sub.1)]or

R_(SET) S₅.

The output of the fifth scaler circuit 422 is coupled to a first inputof a second two-input comparator circuit 424. The output signal S₄ ofthe seventh digital subtraction circuit 418 is coupled to a second inputof the second two-input comparator circuit 424. The second two-inputcomparator circuit 424 is preferably of the same type as that previouslydescribed with respect to the first two-input comparator circuit 66which generates an output signal when the magnitude of the signalapplied to the first input exceeds the magnitude of the signal appliedto the second input. Consequently, the second two-input comparatorcircuit 424 generates an output signal when the magnitude of the signal

    R.sub.SET [Δi.sub.A (t.sub.1)V.sub.r (t.sub.2)-Δi.sub.A (t.sub.2)V.sub.r (t.sub.1)]

exceeds the magnitude of the signal

    [v.sub.A (t.sub.1)V.sub.r (t.sub.2)-v.sub.A (t.sub.2)V.sub.r (t.sub.1)]

or R_(SET) S₅ >S₆.

The output of the second two-input comparator circuit 424 is coupled tothe input of a second counter 426. In the preferred embodiment, thesecond counter 426 is of the same type as that previously described withrespect to the first counter 68 which provides a count signal uponreceipt of a signal from the second two-input comparator circuit 424.The count signal is incremented by one count if the signal from thesecond two-input comparator circuit 424 is present during the nextsucceeding sampling interval; otherwise, the count signal is reset tozero. The count signal is incremented by one count upon receipt of asignal from the second two-input comparator circuit 424 during eachsucceeding sampling interval. The count signal is reset to zerofollowing any sampling interval during which a signal is not receivedfrom the circuit 424.

The count signal from the second counter 426 is coupled to the input ofa second comparator circuit 428. The second comparator circuit 428 ispreferably of the same type as that previously described with respect tothe first comparator circuit 70 which generates an output signal O₂,which is a second operate signal in the preferred embodiment, when themagnitude of the input signal exceeds a predetermined value.Consequently, the second comparator circuit 428 will generate the secondoperate signal O₂ when the magnitude of the count signal exceeds apredetermined value, for example 3 in the preferred embodiment. Thismeans that in the preferred embodiment, the second operate signal O₂will be generated upon detection of a signal from the second two-inputcomparator circuit 424 during at least three consecutive samplingintervals.

Referring now to FIG. 5, the first operate signal O₁ is coupled to thefirst input of a two-input AND gate 250 and the second operate signal O₂is coupled to the second input of the two-input AND gate 250. The outputof the two-input AND gate 250 is a trip signal which is generated uponcoincidence of the first operate signal O₁ and the second operate signalO₂. The trip signal is preferably utilized to enable the operation of acircuit breaker or other transmission line interruption means.

The preferred embodiment of the apparatus for providing distanceprotection and distance measurement for a high voltage transmissionline, as depicted in FIGS. 1, 2, 3, 4 and 5, operates as follows. Whenthere is no fault on the line, and the load remains substantiallyconstant, the signal ##EQU7## is equal to the signal i_(A) (t).Consequently, the output Δi_(A) (t) from the first subtract circuit 26is equal to 0. As a result, the signal i_(f) (t) output from the firsttwo-input adder 34 is also equal to 0. Accordingly, the output signali_(f) (t₁) and i_(f) (t₂) from the first sampler/buffer circuit 42 arealso 0. Therefore, the output signals from the first 48, second 50,third 52 and fourth 54 multipliers are 0 which means that the inputsignals to the first comparator 66 are 0 as well. Since both inputsignals are 0, the first comparator 66 will not produce an output signalwhich thus precludes the generation of the first operate signal O₁ fromthe output of the first comparator 70.

Since the output Δi_(A) (t) from the first subtract circuit 26 is equalto 0, the output signals Δi_(A) (t₁) and Δi_(A) (t₂) from the seventhsampler/buffer circuit 402 are also 0. Therefore, the output signalsfrom the ninth 408 and tenth 410 multipliers are 0 which means that theoutput signal S₃ from the sixth subtract circuit 416 is 0 as well. SinceS₃ is 0, the output R_(SET) from the fifth scaler circuit 422 is also 0.As indicated previously, the second two-input comparator circuit 424will generate an output when R_(SET) S₃ >S₄. Since R_(SET) S₃ is 0, thesecond comparator 224 will not produce an output signal which thusprecludes the generation of the second operate signal O₂ from the outputof the second comparator 228. Since the generation of the first outputsignal O₁ and the second output signal O₂ is precluded, the AND gate 250will not produce a trip signal.

Assuming now a fault on phase A, the output Δi_(A) (t) from the firstsubtract circuit 26 will now be equal to the fault current since theoutput of subtract circuit 26 is the total postfault current (i.e. loadcurrent plus fault current) minus the prefault current (load current)occurring at h/f second prior to the occurrence of the fault. SinceΔi_(A) (t) is no longer zero, the comparator 66 will generate an outputsignal when

    n.sub.set [V.sub.r (t.sub.1)i.sub.f (t.sub.2)-V.sub.r (t.sub.2)i.sub.f (t.sub.1)]>[V.sub.A (t.sub.1)i.sub.f (t.sub.2)-VA(t.sub.2)i.sub.f (t.sub.1)]

or n_(set) S₁ >S₂. This means that the A phase fault of this example hasoccurred within the relay reach as set by the value of the constantn_(SET) as previously described.

Similarly, the second two-input comparator 424 will generate an outputsignal when R_(SET) S₃ >S₄. This means that the A phase fault of thisexample has occurred within the resistance reach of the relay as set bythe value of the constant R_(SET) as previously described. Since a Aphase fault has been assumed, the output signal from the first two-inputcomparator 66 and the output signal from the second two-input comparator424 will each remain during the three consecutive sampling intervals;consequently, the first 70 and second 428 comparators will generateoperate signals O₁ and O₂ respectively. The requirement that thetwo-input comparator output signals remain during consecutive samplingintervals is to ensure that an operate signal is generated only foractual faults and is not based on transient or spurious signals.

Since a phase A fault has been assumed in this example, the outputsignals O₁ and O₂ from the first 70 and second 428 comparators will begenerated concurrently. Consequently, the AND gate 250 depicted in FIG.5, will generate a trip signal which is utilized by the protectionsystem to trip circuit breakers thereby isolating the faulted phaseAlso, since Δi_(A) (t) is no longer zero, the divider circuit 220 (seeFIG. 3) will generate a signal n which is a function of the distancefrom the relay to the fault and which is equal to ##EQU8##

Similarly, since Δi_(A) (t) is no longer 0, the second divider circuit420 (see FIG. 4) will generate a signal R_(fA) which is a function ofthe fault resistance and which is equal to ##EQU9##

When there is no fault on the line, but the load current changes, thesignal Δi_(A) (t) will be equal to the magnitude of the change in loadcurrent since the output of the subtract circuit 26 is proportional tothe post-load change current minus the pre-load change current. However,the n_(SET) and R_(SET) constants have been selected to ensure thatthere will be no output from the first 66 and second 424 two-inputcomparators for changes in load currents which are not due to faultswithin the reach of the relay. This can best be explained by referenceto FIG. 6 which depicts the relay characteristic plotted on an L-Rdiagram As can be seen, when

    n.sub.SET [v.sub.r (t.sub.1)i.sub.f (t.sub.2)-v.sub.r (t.sub.2)i.sub.f (t.sub.1)][v.sub.A (t.sub.1)i.sub.f (t.sub.2)-v.sub.A (t.sub.2)i.sub.f (t.sub.1)]and

    R.sub.SET [v.sub.r (t.sub.1)Δi.sub.A (t.sub.2)-v.sub.r (t.sub.2)Δi.sub.A (t.sub.1)]>[v.sub.A (t.sub.1)Δi.sub.A (t.sub.2)-v.sub.A (t.sub.2)Δi.sub.A (t.sub.1)]

the relay will not operate since that load characteristic falls withinthe zone of operation as shown in FIG. 6

    When n.sub.SET [v.sub.r (t.sub.1)i.sub.f (t.sub.2)-v.sub.r (t.sub.2)i.sub.f (t.sub.1)][v.sub.A (t.sub.1)i.sub.f (t.sub.2)-v.sub.A (t.sub.2)i.sub.f (t.sub.1)]and

    R.sub.SET [v.sub.r (t.sub.2)Δi.sub.A (t.sub.1)-v.sub.r (t.sub.1)Δi.sub.A (t.sub.2)]>v.sub.A (t.sub.1)V.sub.r (t.sub.2)-v.sub.A (t.sub.2)V.sub.r (t.sub.1)]

the relay will not operate since the load current falls outside of thezone of operation shown in FIG. 6.

As can be seen from the diagram of FIG. 6, n_(SET) line can be tilted(see dotted line) in order to provide a slope to the relay reach. Thistilt angle α is adjustable as provided by the differentiator 32 andscaler 36 of FIG. 1 where is scale function of the scaler 36 is tanα/2πf.

Referring now to FIG. 7, there is shown a block diagram of a variableresistance reach portion of the apparatus of the present invention Theoutput signal Δi_(A) (t) from the first digital subtraction circuit 26(see FIG. 1) is coupled to the input of a tenth sampler/buffer circuit302. The tenth sampler/buffer circuit 302 is of the same type as thepreviously described first 42 through ninth 406 sampler/buffer circuits.Accordingly, the tenth sampler/buffer circuit 302 has two outputs, thefirst of which is equal to the magnitude of the input signal sampled atthe first time t₁, and the second of which is equal to the magnitude ofthe input signal sampled at the second time t₂. Consequently, theoutputs of the tenth sampler/buffer circuit 302 is a first signal Δi_(A)(t₁) which is the input signal Δi_(A) (t) sampled at the first time t₁ ;and the second output is a signal Δi_(A) (t₂) which is equal to theinput signal Δi_(A) (t) sampled at the second time t₂.

The output signal Δi_(A) (t₁) from the tenth sampler/buffer circuit 302is coupled to one input of a maximum computation circuit 304 and oneinput of a minimum computation circuit 306. The output signal Δi_(A)(t₂) from the tenth sampler/buffer circuit 302 is coupled to a secondinput of the maximum computation circuit 304 and a second input of theminimum computation circuit 306. The maximum computation circuit 304 isa circuit which compares the magnitude of the two-input signals andprovides an output signal which is equal to the maximum value of the twocompared input signals. Consequently, the output signal from the maximumcomputation circuit 304 is the signal Δi_(A) (t)MAX. The minimumcomputation circuit 306 is a circuit which compares the magnitudes ofthe two-input signals and provides an output which is equal to theminimum of the input signals. Consequently, the output of the minimumcomputation circuit 306 is the signal Δi_(A) (t)MIN.

The output signal Δi_(A) (t)MAX from the maximum computation circuit 304is coupled to one input of a third two-input adder 308. The outputsignal Δi_(A) (t)MIN is coupled to the second input of the thirdtwo-input adder 308. The third two-input adder 308 is preferably thesame type as the previously described first 34 and second 42 two-inputadders. Accordingly, the output of the third two-input adder 308 is asignal having a magnitude which is substantially equal to the sum of themagnitudes of the two input signals. Consequently, the output of thethird two-input adder 308 is the signal 2ΔI_(A) pk. The output signal 2ΔI_(A) pk from the third two-input adder 308 is coupled to the input ofa sixth scaler circuit 310. The sixth scaler circuit 310 is the sametype as the previously described first 3, second 36, third 38, fourth 64and fifth 422 scaler circuits. Accordingly, the sixth scaler circuit 310has an output which is equal to the input multiplied by a predeterminedscaling function. In the preferred embodiment, the scaling function ofthe sixth scaler circuit 310 is the quantity 0.5; consequently, theoutput of the sixth scaler circuit 310 is the signal ΔI_(A) pk, which iscoupled to one input of a thirteenth two-input multiplier 312.

The thirteenth two-input multiplier 312 is preferably the same type asthe first 48 through twelfth 414 two-input multipliers previouslydescribed Accordingly, the thirteenth two-input multiplier 312 producesa digital output signal having a magnitude which is equal to themagnitude of the first input signal multiplied by the magnitude of thesecond input signal. The output signal S4 from the fifth digitalsubtraction circuit 218 (see FIG. 3) is coupled to the second input ofthe thirteenth two-input multiplier 312. Consequently, the output signalfrom the thirteenth two-input multiplier 312 is the signal ΔI_(A) pkS₄.The output signal ΔI_(A) pkS₂ from the thirteenth multiplier 312 iscoupled to one input of a third two-input comparator circuit 314.

The output signal S₃ from the fourth digital subtraction circuit 216(see FIG. 3) is coupled to the input of a seventh scaler circuit 316.The seventh scaler circuit 316 is preferably the same type as thatpreviously described with respect to the first 30, second 36, third 38,fourth 64, fifth 222 and sixth 310 scaler circuits, having an outputwhich is equal to the input multiplied by a predetermined scalingfunction In the preferred embodiment, the scaling function of theseventh scaler circuit 316 is the quantity V_(SET) which is a constantdetermined by the desired relay reach. Consequently, the output of theseventh scaler circuit 316 is the signal V_(SET) S₃, which is coupled tothe second input of the third two-input comparator circuit 314.

The third two-input comparator circuit 314 is preferably the same typeas that previously described with respect to the first 66 and second 424two-input comparator circuits, each of which generates an output signalwhen the magnitude of the signal applied to the first input exceeds themagnitude of the signal applied to the second input. Consequently, thethird two-input comparator circuit 314 generates an output signal whenthe magnitude of the signal V_(SET) S₃ >ΔI_(A) pkS₄. Since signal S₃ isequal to [v_(r) (t₁)Δi_(A) (t₂)-v_(r) (t₂)Δi_(A) (t₁)] and signal S₄ isequal to [v_(A) (t₁)Δi_(A) (t₂)-v_(A) (t₂)Δi_(A) (t₁)], the thirdcomparator 314 will generate an output signal when

    V.sub.SET [v.sub.r (t.sub.1)Δi.sub.A (t.sub.2)-v.sub.r (t.sub.2)Δi.sub.A (t.sub.1)]>ΔI.sub.A pk[v.sub.A (t.sub.1)Δi.sub.A (t.sub.2)-v.sub.A (t.sub.2)Δi.sub.A (t.sub.1)].

The output signal from the third two-input comparator circuit 314 iscoupled to the input of a third counter 318. In the preferredembodiment, the third counter 318 is the same type as that previouslydescribed with respect to the first 68 and second 426 counters each ofwhich provides a count signal upon receipt of a signal from theirrespect two-input comparator circuits. Accordingly, the output countsignal is incremented by one count if the signal from the thirdtwo-input comparator circuit 314 is present during the next succeedingsampling interval; otherwise, the output count signal is reset to 0. Theoutput count signal is incremented by one count upon receipt of a signalfrom the third two-input comparator circuit 314 during each succeedingsampling interval. The count signal is reset to 0 following any samplinginterval during which the signal is not received from the comparatorcircuit 314.

The output count signal from the third counter 318 is coupled to theinput of third comparator circuit 320. The third comparator circuit 320is preferably the same type as that previously described with respect tothe first 70 and second 428 comparator circuits each of which generatesan output signal when the magnitude of the input signal exceeds apredetermined value. Accordingly, the third comparator 320 will generatean output signal O₃, which is a third operate signal in the preferredembodiment, when the magnitude of the input signal exceeds apredetermined value, for example 3, in the preferred embodiment. Thismeans that in the preferred embodiment, the third operate signal O₃ willbe generated upon detection of a signal from the third two-inputcomparator circuit 314 during at least three consecutive samplingintervals.

The third operate signal O₃, since it is generated when ΔI_(A) pkR_(FA)<V_(SET) (relay setting), where ΔI_(A) pk is the peak value of ΔI_(A),gives the relay a variable reach characteristic along the resistive axissimilar to that obtained with a variable MHO characteristic.Consequently, the optimum relay tripping characteristic is preferably acombination of the following criteria: ##EQU10##

This is implemented by coupling the third operate signal O₃ to one inputof an AND gate and coupling O₂ MAX (the second operate signal O₂adjusted for maximum R_(F) reach) to the other input of the two-inputAND gate. The output of the two-input AND gate is coupled to one inputof a two-input oR gate. The signal O₂ MIN (R_(SET) set for minimum R_(F)reach) is coupled to the other input of the two-input OR gate. Theoutput of the two-input OR gate is coupled to the second input of thetwo-input AND gate 250 depicted in FIG. 5 with the first operate signalO₁ being coupled to the first input of AND gate 250 as shown in FIG. 5.

Referring to FIG. 14, there is shown a block diagram of a preferredembodiment of a fault resistance R_(f) measurement portion generallydesignated 700, of the present invention. The resistance measurementportion 700 comprises an adder 702 having a first input and a secondinput. The signal Δi_(A), which is generated as shown in FIG. 1, iscoupled to the first input of the adder 702. A signal Δi_(B), which isgenerated by a relay in accordance with the present invention, andparticularly is described in FIG. 1, which relay is located in secondposition B remote from the position A of a first relay as describedherein, is coupled to the second input of the adder 702. In a preferreduse environment a first distance relay in accordance with the presentinvention is located a first position A and a second distance relay, inaccordance with the present invention is located a second position Bwith the protected zone being defined by the transmission line locatedbetween positions A and B.

The adder 702 is preferably of the same type as that previouslydescribed with respect to the first two input adder 34, and having anoutput signal whose magnitude is equal to the sum of the input Δi_(A)and Δi_(B). Accordingly, the output of the adder 702 is equal to Δi_(A)+Δi_(B).

The output from the adder 702 is coupled to a divisor input of a divider704. The Δi_(A) signal is coupled to the dividend input of the divider704. In a preferred embodiment, the divider 704 is the same type as thepreviously described first digital divider circuit 20; having an outputsignal whose magnitude is equal to the quotient of the signal Δi_(B)applied to the divisor input Δi_(A) +Δi_(B) applied to the divisorinput. Consequently, the output signal from the divider circuit 704 issubstantially equal to ##EQU11## The output of the divider circuit 704is coupled to one input of a two input multiplier circuit 706. Thesignal R_(fA), which is generated as previously described in connectionwith FIG. 4, is coupled to the second input of the two input multiplier706. In the preferred embodiment, the two input multiplier 706 is thesame type as the first two input multiplier 48 previously described;having an output signal whose magnitude is equal to the magnitude of thefirst input signal ##EQU12## multiplied by the magnitude of the secondinput signal R_(fA). Consequently, the output Rf of the two inputmultiplier circuit 706 is equal to The signal R_(F) is a function of thefault resistance recurring at the fault location; that is, the magnitudeof R_(f) is proportional to the magnitude of the fault resistancemeasured at the fault location and the angle of the signal R_(F) issubstantially equal to the fault resistance angle. As previouslydescribed the magnitude of the signal R_(fA) is proportional to themagnitude of the fault resistance measured at the relay location and theangle of the signal R_(fA) is substantially equal to the faultresistance angle.

Referring now to FIG. 15, there is shown a block diagram of an alternatepreferred embodiment of the resistance measurement portion, generallydesignated 800, of the present invention. The fault resistancemeasurement portion 800 comprises a two input multiplier 802 and a twoinput adder 804. The signal R_(fA) generated as previously describedwith respect to FIG. 4, is coupled to one input of the two inputmultiplier 802 and one input of the two input adder 804. A signal R_(fB)generated by the relay located at position B, is coupled to the secondinput of the two input multiplier 802 and the second input multiplieradder 804. The signal R_(fB) is generated in the same manner aspreviously described with respect to FIG. 4 for the signal R_(fA) . Inthe preferred embodiment, the two input multiplier 802 is the same typeas the previously described two input multiplier 48, which produces anoutput signal having a magnitude which is equal to the magnitude of thesignal R_(fA) applied to the first input multiplied by the signal R_(fB)applied to the second input. Consequently, the output of the two inputmultiplier 802 is the signal R_(fA) ×R_(fB). The second adder 804 ispreferably the same type as the previously described two input adder 34,having an output signal whose magnitude is equal to the sum of thesignal R_(fA) applied to the first input plus the signal R_(fB) appliedto the second input. Accordingly, the output of the two input adder 804is the signal R_(fA) +R_(fB), which signal is coupled to the divisorinput of a divider 806. The output of the multiplier, R_(fA) ×R_(fB) iscoupled to the dividend input of the divider 806. The divider 806 ispreferably the same type as the previously described divisor 220 havingan output R_(F), which is equal to the signal R_(fA) ×R_(fB) applied tothe dividend input divided by the signal R_(fA) +R_(fB) applied to thedivisor input. Consequently, the output R_(F) of the divider 806 isequal to ##EQU13## the signal R_(F) is a function of the actual faultresistance; as previously described; that is, the magnitude of R_(F) isproportional to the magnitude of the fault resistance measured at thefault location, and the angle of the signal R_(F) is substantially equalto the fault resistance angle.

Referring now to FIG. 8, there is shown a current and voltage processingportion of an alternate preferred embodiment of the apparatus forproviding distance protection and distance measurement for a highvoltage transmission line in accordance with the present invention. Thealternating current electric power transmission line is generallydesignated 500. As with the previous description, the following detaileddescription will be described with respect to the A phase (A) and ground(G) only for purposes of simplicity and clarity, realizing thatalternating current electrical power transmission lines normallycomprise three phases and ground. Consequently, it should be understoodthat the following description also applies with respect to the B phaseand the C phase, as well as relays connected between phases.

Associated with the A phase is means 502 for sensing current in thatphase as well as means 504 for sensing voltage on that phase. Such meansare of the same type as those previously described and referred to asmeans 12 and means 14 respectively.

The output of the current sensing means 502, which is a signal i_(A) (t)proportional to the current flowing in the A phase, is coupled to theinput of a first low pass filter 506. The output of the voltage sensingmeans 504, which is a signal v_(A) (t) proportional to the phase A toground voltage, is coupled to the input of a second low pass filter 508.In the preferred embodiment, the first 506 and second 508 low passfilters are preferably of the same type as the first 16 and second 18low pass filters previously described.

The output of the first low pass filter 506 is coupled to the input of afirst sample and hold circuit 510. The output of the second low passfilter 508 is coupled to the input of a second sample and hold circuit512. The first 510 and second 512 sample and hold circuits each samplethe voltage at its input and holds the sample for a predetermined timeat its output as is known in the art of analog circuit design.

The output of the first sample and hold circuit 510 is coupled to oneinput of a analog multiplexer 514. The output of the second sample andhold circuit 512 is coupled to a second input of the analog multiplexer514. The analog multiplexer 5-4 samples the inputs and presents them tothe output one at a time as is known in the art of analog circuitdesign. In the preferred embodiment, the analog multiplexer 514 is atype HI-508/HI-509 Single 8/Differential 4 Channel CMOS AnalogMultiplexer manufactured by the Harris Semiconductor Company anddescribed in pages 4-25 through 4-29 of the Harris SemiconductorBulletin, which pages are incorporated by reference into thespecification as fully set forth herein. The output of the analogmultiplexer 514 is coupled to the input of an analog to digitalconverter 516. The analog to digital converter 516 is preferably of thesame type as the previously described analog to digital converter 20 andthe output of the analog to digital converter 5I6 is a digitized versionof the analog input signal.

The output of the analog to digital circuit 516 is coupled to the inputof a digital signal processor 518. The digital signal processor 518 ispreferably a digital computer which is programmed to compute thediscreet Fourier transform of the input signal. A preferred embodimentof such a digital signal processor is set forth in the book entitled"Digital Signal Processing", A. V. Oppenheim and R. W. Shafer, publishedin 1975 by Prentise-Hall, Englewood Cliffs, N. J. and in particularchapter 6 of that book entitled "Computation of the Discreet ForneyTransform".

The following digital signals are provided by the digital signalprocessor 518. V_(A) which is a signal proportional to the phase A toground voltage. I_(A) which is a signal proportional to the phase Acurrent. α which is a signal proportional to the phase angle betweenV_(A) and I_(A). γ which is a signal proportional to the angle betweenΔI_(A) and I_(A) where ΔI_(A) is equal to the magnitude of the phase Acurrent I_(A) occurring at a second time period minus the magnitude ofthe phase A current I_(A) occurring at a first time period, the secondtime period occurring later than the first time period. β which is asignal which is proportional to the phase angle of the line impedance.

The signal ΔI_(A) can also be generated by the digital signal processor518 as shown in FIG. 8. Alternatively, the signal ΔI_(A) can begenerated using a buffer circuit and a subtraction circuit such asbuffer circuit 24 and subtraction circuit 26 previously described withrespect to FIG. 1.

Referring now to FIG. 9, the output signal V_(A) from the digital signalprocessor 5I8 (see FIG. 8) is coupled to one input of a first multiplier520. The output signal I_(A) of the digital signal processor 518 iscoupled to one input of a second multiplier 522. As shown in

FIG. 9, the signal α, from the digital signal processor 518 is coupledto the positive input of a first two-input adder 524. The signal β, fromthe digital signal processor 5-8, is coupled to the positive input of asecond two-input adder 526. The signal γ, from the digital signalprocessor 518, is coupled to the negative input of the first two-inputadder 524 and the negative input of the second two-input adder 526. Inthe preferred embodiment, the first 524 and second 526 two-input addersare of the same type as the previously described two-input adder 26.

The output of the first two-input adder 524, is a signal α-γ which isproportion to the difference between the phase angle α and the phaseangle γ. The signal is coupled to the input of a first scaler circuit528. The first scaler circuit 528 is of the same type as the previouslydescribed first 30, second 36 and third 38 scaler circuits having anoutput which is equal to the magnitude of the input signal multiplied bythe scaling function which, in the preferred embodiment, is equal to thesine function of the input quantity. Consequently, the output of thefirst scaler 528 is a signal which is proportional to sin(α-γ) which iscoupled to a second input of the first multiplier 520. Since the inputsto the first multiplier 520 are the signals V_(A) and sin(α-γ) theoutput of the first multiplier 520 is a signal proportional to V_(A)sin(α-γ) and is coupled to a dividend input of a divider circuit 530.The divider circuit 530 provides an output signal which is proportionalto the magnitude of the dividend input signal divided by the magnitudeof the divisor input signal.

The output of the second adder circuit 526 , which is a signalproportional to β-γ is coupled to the input of a second scaler circuit532. The second scaler circuit 532 is of the same type as the previouslydescribed first 30, second 36 and third 38 scaler circuits having anoutput which is equal to the magnitude of the input signal multiplied bythe scaling function. Since the scale function for the second scalercircuit 532 is the sine function of the input quantity, the outputsignal from the second scaler circuit 532 is sin(β-γ). This signal iscoupled to a second input of the second multiplier circuit 522.Consequently, the output of the second multiplier circuit 522 is asignal proportional to I_(A) sin(β-γ) and is coupled to the divisorinput of the divider circuit 128. Consequently, the output of thedivider circuit 128 is a signal Z_(L) which is equal to ##EQU14## Thesignal Z_(L) is representative of the magnitude of the impedance of thetransmission line within the reach of the relay.

Referring now to FIG. 10, there is shown the distance protection,distance reach portion of the alternate preferred embodiment of theapparatus of the present invention. The output signal V_(A) from thedigital signal processor 518 (see FIG. 8) is coupled to one input of athird multiplier 534. The output signal I_(A) from the digital signalprocessor 518 is coupled to one input of a fourth multiplier 536. In thepreferred embodiment, the third 534 and fourth 536 multipliers are ofthe same type as the previously described multipliers for example firstmultiplier 48.

The signal γ is coupled to the input of a third scaler circuit 538. Thethird scaler circuit 538 is of the same type as the previously describedfirst and second scaler circuits 528 and 532. The output signal γ' ofthe third scaler circuit 538 is equal to the input signal multiplied bya scale function which, for the third scaler 538, is the quantity ±εwhich is proportional to a predetermined "tilt" angle as previouslydescribed. The output of the third scaler 538 is coupled to the negativeinputs of a third adder 138 and a fourth adder 140. In the preferredembodiment, the third adder 540 and fourth adder 542 are each of thesame type as the previously described first 524 and second 526 adders(see FIG. 9).

The signal α from the digital signal processor 518 (see FIG. 8) iscoupled to the positive input of the third adder 540. The signal β fromthe digital signal processor 518 is coupled to the positive input of thefourth adder 542. The output of the third adder 540 is the signal α-γ'and is coupled to the input of a fourth scaler circuit 544. The outputof the fourth adder 542 is the signal β-γ' and is coupled to the inputof a fifth scaler 546. The fourth 544 and fifth 546 scaler circuits areeach of the same type as the previously described first 528 and second532 scaler circuits (see FIG. 9), with each scaler having a scale factorwhich is proportional to the sine function of the input. Consequently,the output of the fourth scaler 544 is the signal sin(α-γ') which iscoupled to a second input of the third multiplier circuit 534. Theoutput of the third multiplier circuit 534 is the signal S₁ which isequal to V_(A) sin(α-γ') and is coupled to one input of a firsttwo-input comparator 548.

The output signal from the fifth scaler 546 is the signal sin(β-γ')which is coupled to a second input of the fourth multiplier 536. Theoutput of the fourth multiplier 536 is the signal S₂ which is equal toI_(A) sin(β-γ') and which is coupled to the input of a sixth scalercircuit 550. The sixth scaler circuit 550 is of the same type as thepreviously described scaler circuits but having a scale function Z_(r)which is proportional to the impedance of the reach of the relay.Consequently, the output of the sixth scaler circuit 550 is a signalZ_(r) I_(A) sin(β-γ') or Z_(r) S₂ which is coupled to the second inputof the two-input comparator 548.

The two-input comparator 548 compares the magnitude of the input signalsS₁ and Z_(r) S₂ and generates an operate signal O₁ when the magnitude ofZ_(r) S₂ is equal to or greater than the magnitude of the input signalS₁. The operate signal O₁ from the first two input comparator 548 iscoupled to an AND gate as subsequently described with respect to FIG.12.

Referring now to FIG. 11, there is shown a block diagram of a distanceprotection, resistance reach and measurement portion of the alternatepreferred embodiment of the apparatus of the present invention. Thesignal V_(A) from the digital signal processor 518 (see FIG. 8) iscoupled to one input of a fifth multiplier circuit 552. The signalΔI_(A) which, as previously described, is equal to the magnitude of theI_(A) signal sampled at a second time minus the magnitude of the I_(A)signal sampled at a first, earlier time, is coupled to one input of asixth multiplier circuit 554. In the preferred embodiment, the fifth andsixth multiplier circuits, 552 and 554, are of the same type as thepreviously described multiplier circuits for example the firstmultiplier circuit 520.

The signal α from the digital signal processor 518 is coupled to thenegative input of a fifth adder circuit 556. The signal γ from thedigital signal processor 518 is coupled to the negative input of a sixthadder circuit 558. In the preferred embodiment, the fifth 556 and sixth558 adder circuits are the same type as the previously described addercircuits 524 and 526 (see FIG. 9). The signal β from the digital signalprocessor 5I8 is coupled to the positive inputs of the fifth addercircuit 556 and the sixth adder circuit 558.

The output of the fifth adder circuit 556, which is the signal β-α, iscoupled to the input of a seventh scaler circuit 560. The output of thesixth adder circuit 558, which is the signal β-α, is coupled to theinput of an eighth scaler circuit 562. In the preferred embodiment, theseventh 560 and eighth 562 scaler circuits are of the same type as thepreviously described scaler circuits, for example the first scalercircuit 528, in that the scale factor is a sine function of the inputquantity. Consequently, the output of the seventh scaler circuit 560 isthe signal sin(β-α) which is coupled to a second input of the fifthmultiplier 552. The output of the eighth scaler circuit 562 is a signalsin(β-α) which is coupled to a second input of the sixth multipliercircuit 554.

The output signal S₃ from the fifth multiplier circuit 552, which isequal to V_(A) sin(β-α), is coupled to the dividend input of a seconddivider circuit 566, and one input of a second two-input comparatorcircuit 568. In the preferred embodiment, the second divider circuit 566is of the same type as the previously described first divider circuit530 (see FIG. 9) having an output signal which is equal to the magnitudeof the dividend input divided by the divisor input The second two-inputcomparator circuit 568 is of the same type as the previously describedfirst two-input comparator circuit 548 (see FIG. 10).

The output signal S₄ from the sixth multiplier 554, which is equal toΔI_(A) sin(β-α), is coupled to the divisor input of the second dividercircuit 566 and the input of a ninth scaler circuit 564. The outputsignal R_(fA) from the second divider 566 is therefore a signal which isequal to ##EQU15## and is proportional to the magnitude of theresistance of that portion of the transmission line within the relayreach. In the preferred embodiment, the ninth scaler circuit 564 is ofthe same type as the previously described fifth scaler circuit 422 (seeFIG. 4) in that the scale function is the quantity R_(set) which isproportional to the desired resistance reach setting.

The output signal from the ninth scaler circuit 564, which is equal toR_(set) ΔI_(A) sin(β-γ), or R_(set) S₄ is coupled to a second input ofthe second two-input comparator circuit 568. The second comparatorcircuit 568 generates an operate signal O₂, which is coupled to an ANDgate as subsequently described with respect to Figure -2, when themagnitude of the signal R_(set) S₄ is equal to or greater than themagnitude of the signal S₃.

Referring now to FIG. 12, the first operate signal O₁ is coupled to thefirst input of a two-input AND gate 580 and the second operate signal O₂is coupled to the second input of the two-input AND gate 580. The outputof the two-input AND gate 580 is a trip signal which is generated uponcoincidence of the first operate signal O₁ and the second operate signalO₂. The trip signal is preferably utilized for enabling the operation ofa circuit breaker or other transmission line interruption means.

The alternate preferred embodiment of the apparatus, as depicted inFIGS. 8, 9, 10 and 11 operates as follows. When there is no fault on aline, and the load remains substantially constant, the signal ΔI_(A) isequal to 0. Also, the phase angle γ between ΔI_(A) and the phase currentI_(A) is also 0. Consequently, the signal Z_(L) from the divider 530(see FIG. 9) is equal to ##EQU16## Since, as previously described, α isproportional to the phase angle between V_(A) and I_(A) and β isproportional to the phase angle of the impedance, and since in thisexample it is assumed there is no fault on the line and the load remainssubstantially constant, the magnitude of Z_(L) will be greater than themagnitude of Z_(set) and an operate signal will not be generated fromthis portion of the system. Likewise, since γ is 0 in this example, thesignal S₁ in FIG. 10 is equal to V_(A) sin(α) and the signal S₂ is equalto Z_(r) I_(A) sin(β). Under these no fault, no load change conditions,the quantity ##EQU17## will be greater than the quantity Z_(r) andtherefore this portion of the system will not generate an operatesignal.

Referring to FIG. 11, S₃, in this example, will be equal to V_(A)sin(β); and S₄ will be equal to 0 since ΔI_(A) is 0. Consequently, themagnitude of the signal S₃ will be greater than the magnitude of thesignal S₄ and the comparator 568 will therefore not generate an operatesignal. Also, since the magnitude of the signal S₄ is 0, the magnitudeof the signal R_(fA) will be much larger than the signal R_(set) ;therefore, this portion of the system will also not generate an operatesignal.

Assuming now a fault on phase A, the signal ΔI_(A) will be equal to thefault current and the signal γ will be proportional to the phase anglebetween the fault current and the prefault current. Since ΔI_(A) and γare no longer 0, the apparatus will generate an operate signal when themagnitude of Z_(L) ; (see FIG. 9) is less than or equal to the magnitudeof the signal Z_(set). Similarly, the comparator 548 (see FIG. 10) willgenerate an operate signal when V_(A) sin(α-γ') is less than or equal tothe signal Z_(r) I_(A) sin(β-γ'), or when the magnitude of the equal S₁is less than or equal to the magnitude of the signal S₂ as shown in FIG.10. Likewise, the comparator 568 will generate an operate signal whenthe signal V_(A) sin(β-γ) is less than or equal to the signal R_(set)ΔI_(A) sin(β-γ) or the magnitude of the signal S₃ is less than or equalto the magnitude of the signal S₄ shown in FIG. 11. Also, the systemwill generate an operate signal when the magnitude of the signal R_(fA)is less than or equal to the magnitude of the signal R_(set). Thislatter means that the A phase fault of this example has occurred withinthe resistance reach of the relay as set by the value of the constantR_(set) as previously described.

When there is no fault on the line, but the load current changes, thesignal ΔI_(A) will be equal to the magnitude of the change in loadcurrent. Likewise, the signal γ will be proportional to the phase anglebetween the current after the load change and the current before theload change. However, the Z_(set) and R_(set) constants have beenselected to ensure that there will be no outputs from the first 548 andsecond 568 comparators respectively for changes in load currents whichare not due to faults within the reach of the relay. This can best beexplained by reference to FIG. 13 which depicts the relay characteristicplotted on an L-R diagram. As can be seen, when either V_(A) sin(α-γ')is greater than Z_(r) I_(A) sin(β-γ') or V_(A) sin(β-γ) is greater thanR_(set) ΔI_(A) sin(β-γ) relay will not operate since the load currentfalls outside of the zone of operation shown in FIG. 13. However, whenZ_(r) I_(A) sin(β-γ') is greater than or equal to V_(A) sin(α-γ') andR_(set) ΔI_(A) sin(β-γ) is greater than or equal to V_(A) sin(β-α), therelay will operate since load characteristic falls within the zone ofoperation as shown in FIG. 13.

As can be seen from the diagram of FIG. 13, the Z_(r) line can be tilted(see dotted line) in order to provide a slope to the relay reach. Thistilt angle ε is adjustable as provide by the scaler 538 (see FIG. 10).

As can be seen from the above description, the apparatus of the presentinvention has improved discrimination between internal/external faultsthereby increasing the reliability of operation and the security of theprotection system. Also, it can be seen that the system provides anaccurate determination of the distance to the fault.

While the present invention has been described with reference to aspecific embodiment thereof, it will be obvious to those skilled in theart that various changes and modifications may be made without departingfrom the invention in its broader aspects. It is contemplated in theappended claims to cover all variations and modifications of theinvention that come within the true spirit and scope of my invention.

What is claimed is:
 1. A protective relay for detecting faults in anelectrical power distribution system, said relay comprising:(a) meansfor receiving signals from an electrical power distribution system,which signals relate to at least one system voltage v and at least onesystem current i; (b) means for generating a signal di/dt which issubstantially equal to a first derivative with respect to time of saidsystem current; (c) means for generating a signal v_(r) which issubstantially equal to the sum of a line resistance R of said powerdistribution system multiplied by said system current i and a lineinductance L multiplied by said di/dt signal; (d) means for generating asignal Δi which is substantially equal to the magnitude of the systemcurrent i measured at a first time subtracted from the magnitude of thesystem current i measured at a second time, said second time occurringlater than said first time; (e) means for generating a signal dΔi/dtwhich is substantially equal to a first derivative with respect to timeof said Δi signal; (f) means for generating a signal i_(f) which issubstantially equal to the sum of the signal Δi plus the signal dΔi/dtmultiplied by a scaling function having a predetermined magnitude; (g)means for generating signals v(t₁), v_(r) (t₁) and i_(f) (t₁) which aresubstantially equal to the magnitude of the signals v, v_(r) and i_(f)respectively occurring at a first time t₁ ; (h) means for generatingsignals v(t₂), v_(r) (t₂) and i_(f) (t₂) which are substantially equalto the magnitude of the signals v, v_(r) and i_(f) respectivelyoccurring at a second time t₂, which second time occurs later than saidfirst time; (i) means for generating a signal S₁ which is substantiallyequal to the signal V_(r) (t₁) multiplied by the signal i_(f) (t₂) minusthe signal v_(r) (t₂) multiplied by the signal i_(f) (t₁); (j) means forgenerating a signal S₂ which is substantially equal to the signal v(t₁)multiplied by the signal i_(f) (t₂) minus the signal v(t₂) multiplied bythe signal i_(f) (t₁); (k) means for providing a signal n_(set) having apredetermined magnitude; and (1) means for generating an output signalO₁ when the magnitude of the signal n_(set) multiplied by the signal S₁is greater than the magnitude of the signal S₂.
 2. A protective relay inaccordance with claim 1 additionally comprising:(a) means for generatinga signal Δi(t₁) which is substantially equal to the magnitude of thesignal Δi occurring at said first time t₁ ; (b) means for generating asignal Δi(t₂) which is substantially equal to the magnitude of thesignal Δi occurring at said second time t₂ ; (c) means for generating asignal S₃ which is substantially equal to the signal v_(r) (t₁)multiplied by the signal Δi(t₂) minus the signal v_(r) (t₂) multipliedby the signal Δi(t₁); (d) means for generating a signal S₄ which issubstantially equal to the signal v(t₁) multiplied by the signal Δi(t₂)minus the signal v(t₂) multiplied by the signal Δi(t₁); and (e) meansfor providing an output signal n which is substantially equal to themagnitude of the signal S₄ divided by the magnitude of the signal S₃. 3.The protective relay in accordance with claim 2 additionallycomprising:(a) means for generating a signal S₅ which is substantiallyequal to the signal v_(r) (t₂) multiplied by the signal Δi(t₁) minus thesignal v_(r) (t₁) multiplied by the signal Δi(t₂); (b) means forgenerating a signal S₆ which is substantially equal to the signal v(t₁)multiplied by the signal v_(r) (t₂) minus the signal v(t₂) multiplied bythe signal v_(r) (t₁); (c) means for providing a signal R_(set) having apredetermined magnitude; and (d) means for generating an output signalO₂ when the magnitude of the signal R_(set) multiplied by the signal S₅is greater than the magnitude of the signal S₆.
 4. The protective relayin accordance with claim 3 additionally comprising:(a) means forgenerating a signal ΔI_(pk) which is substantially equal to a peakmagnitude of the signal ΔI; (b) means for providing a signal V_(set)having a predetermined magnitude; and (c) means for generating an outputsignal when the magnitude of the signal V_(set) multiplied by the signalS₃ is greater than the magnitude of the signal ΔI_(pk) multiplied by thesignal S₄.
 5. A protective relay for detecting faults in an electricalpower distribution system, said relay comprising:(a) means for receivingsignals from an electrical power distribution system, which signalsrelate to at least one system voltage v an at least one system currenti; (b) means for generating a signal Δi which is substantially equal tothe magnitude of the system current i measured at a first timesubtracted from the magnitude of the system current i measured at asecond time, said second time occurring later than said first time; (c)means for generating a signal α which is proportional to a phase anglebetween said system voltage v and said system current i; (d) means forgenerating a signal β which is proportional to a phase angle of a lineimpedance of said electrical power distribution system; (e) means forgenerating a signal γ, which is proportional to a phase angle betweensaid system current i and said signal ΔI; (f) means for generating asignal γ' which is substantially equal to the signal γ multiplied by ascaling function ε having a predetermined magnitude; (g) means forgenerating a signal which is substantially equal to the sine function ofthe signal α minus the signal γ'; (h) means for generating a signalwhich is substantially equal to a sine function of the signal β minusthe signal γ'; (i) means for generating a signal S₁ which issubstantially equal to said system voltage v multiplied by the sinefunction of the signals α minus γ'; (j) means for generating a signal S₂which is substantially equal to the system current i multiplied by thesine function of the signals β minus γ'; (k) means for providing asignal Z_(r) having a predetermined magnitude; and (1) means forgenerating an output signal when the magnitude of the signal Z_(r)multiplied by the signal S₂ is equal to or greater than the magnitude ofthe signal S₁.
 6. The protective relay in accordance with claim 5additionally comprising:(a) means for generating a signal which issubstantially equal to the sine function of the signal α minus thesignal γ; (b) means for generating a signal which is substantially equalto the sine function of the signal β minus the signal γ; (c) means forgenerating a first signal which is substantially equal to the magnitudeof the signal v multiplied by the magnitude of the sine function of thesignals α minus γ; (d) means for generating a second signal which issubstantially equal to the magnitude of the signal i multiplied by themagnitude of the sine function of the signals β minus α; and (e) meansfor providing an output signal Z_(L) which is substantially equal to themagnitude of the first signal divided by the magnitude of the secondsignal
 7. The protective relay in accordance with claim 6 additionallycomprising:(a) means for providing a signal which is substantially equalto the sine function of the signal β minus the signal α; (b) means forproviding a signal S₃ which is substantially equal to the magnitude ofthe signal v multiplied by the magnitude of the sine function of thesignals β minus α; (c) means for providing a signal S₄ which issubstantially equal to the magnitude of the signal Δi multiplied by themagnitude of the sine function of the signals β minusγ; (d) means forproviding a signal R_(set) having a predetermined magnitude; and (e)means for generating an output signal when the magnitude of the signalR_(set) multiplied by the signal S₄ is greater than the magnitude of thesignal S₃.
 8. The protective relay in accordance with claim 7additionally comprising means for generating a signal R_(fA) which issubstantially equal to the magnitude of the signal S₃ divided by themagnitude of the signal S₄.
 9. An apparatus for measuring distance to afault in an electrical power distribution system, said apparatuscomprising:(a) means for receiving signals from an electrical powerdistribution system, which signals relate to at least one system voltagev and at least one system current i; (b) means for generating a signalΔi which is substantially equal to the magnitude of the system currentprior to the occurrence of a fault subtracted from the magnitude of thesystem current following occurrence of the fault; (c) means forgenerating a signal v_(r) which is substantially equal to a voltagemeasured across a line replica impedance; (d) means for generating asignal R_(fA) having an angle which is substantially equal to a faultresistance angle and (e) means for providing an output signal n which isrelated to the distance to the fault and which is substantially equal tothe magnitude of the system voltage v minus the magnitude of the signalΔi multiplied by the signal R_(fA) divided by the signal v_(r).
 10. Adistance relay responsive to the conditions of a fault on an alternatingcurrent power transmission line, said distance relay including means formeasuring distance to a fault on said transmission line, said distancemeasuring means comprising:(a) means for receiving the signal whichrelate to a transmission line voltage v and a transmission line currenti; (b) means for generating a signal Δi which is related to themagnitude of the transmission line current prior to occurrence of afault on the transmission line subtracted from the magnitude of thetransmission line current following occurrence of the fault; (c) meansfor generating a signal v_(r) which is related to said transmission linecurrent multiplied by a predetermined replica impedance; and (d) meansfor generating a signal n related to the distance to the fault, whichsignal is substantially equal to ##EQU18## where v(t₁), v_(r) (t₁) andΔi(t₁) are the signals v, v_(r) and Δi occurring at a first time t₁, andv(t₂), v_(r) (t₂) and Δi(t₂) are the signals v, v_(r) and Δi occurringat a second time t₂ which is later than said first time t₁.
 11. Adistance relay in accordance with claim 10 additionally includingvariable distance reach means comprising:(a) means for establishing apredetermined minimum distance reach n₁ ; (b) means for establishing apredetermined maximum distance reach n₂ ; (c) means for generating asignal S_(SETd) which is related to a variable distance reach; (d) meansfor generating a signal ni_(pk) where i_(pk) is substantially equal to apeak magnitude of the transmission line current i; and (e) means forgenerating a trip signal when n is less than or equal to n₁, or ni_(pk)is less than or equal to v_(SETd) and n is less than or equal to n₂. 12.A distance relay in accordance with claim 11 including means forgenerating a signal R_(fA) which is substantially equal to ##EQU19## andwhich is substantially in phase with the fault resistance.
 13. Adistance relay in accordance with claim 12 additionally including meansfor generating a variable resistance reach, said variable resistancereach means comprising:(a) means for generating a signal R_(SET1)related to a predetermined minimum resistance reach; (b) means forgenerating a signal Δi_(pk) which is related to a peak magnitude of theΔi signal; (c) means for generating a signal V_(SETr) which is relatedto a variable resistance reach; (d) means for generating a signalR_(SET2) which is related to a predetermined maximum resistance reach;and (e) means for generating a trip signal when the signal R_(fA) isless than or equal to the signal R_(SETa), or when the signal Δi_(pk)multiplied by the signal R_(fA) is less than the signal V_(SET) and thesignal R_(fA) is less than or equal to the signal R_(SET2).
 14. Adistance relay in accordance with claim 13 additionally including meansfor generating a signal R_(F) related to the magnitude of faultresistance, which signal is substantially equal to ##EQU20## whereΔi_(B) is related to magnitude of the system current i measured at asecond end of the transmission line prior to occurrence of a faultsubtracted from the magnitude of the system current measured at thesecond end of the transmission line following a occurrence of a fault.15. A distance relay in accordance with claim 13 additionally includingmeans for generating a signal R_(F) related to the magnitude of thefault resistance, which signal is equal to ##EQU21## where R_(fB) isrelated to the magnitude of the fault resistance measured at a secondend of the transmission line, and having an angle which is substantiallyequal to the fault resistance angle.